1. Field of the Invention
The present invention relates to a delay lock loop circuit, and more particularly to a delay lock loop circuit capable of automatically protecting itself when an external clock signal having a frequency that is out of the range of operable frequencies of the delay lock loop circuit is input thereto.
2. Description of the Related Art
FIG. 1 illustrates a conventional delay lock loop circuit. Referring to FIG. 1, a conventional delay lock loop circuit is configured in a double loop structure that includes a reference loop 10 and a fine loop 20. The reference loop 10 receives an external clock signal CLK, and outputs n (where n is a positive integer) output signals RLOUT which have the same frequency as that of the external signal CLK and have different phases with respect to each other. The fine loop 20 generates an internal clock signal ICLK having phase that is similar to that of the external clock signal CLK in response to the output signals RLOUT of the reference loop 10.
Such a conventional delay lock loop circuit has an associated disadvantage in that it can perform an excessive number of extraneous operations when an external clock signal CLK having a frequency that is out of the operable frequency range of the delay lock loop circuit is applied thereto.